Product Summary
The ADC0 subsystem for the C8051F340 devices consists of two analog multiplexers (referred to collec-tively as AMUX0), and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configured under software control via the Special Function Registers shown in Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured to measure voltages at port pins, the Temperature Sensor output, or V;DD with respect to a port pin, VREF, or GND. The connec-tion options for AMUX0 are detailed in SFR Definition 5.1 and SFR Definition 5.2. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN ) is set to logic 1. The ADC0 sub-system is in low power shutdown when this bit is logic 0.
Parametrics
2974.45 Kbytes
Features
(1)10-Bit ADC (C8051F340); (2)- Two comparators; (3)- Internal voltage reference; (4)- Brown-out detector and POR Circuitry; (5)USB Function Controller:USB specification 2.0 compliant;Full speed (12 Mbps) or low speed (1.5 Mbps) operation;Integrated clock recovery; no external crystal required for full speed or low speed;Supports eight flexible endpoints 1 kB USB buffer memory;Integrated transceiver; no external resistors required;
Image | Part No | Mfg | Description | Pricing (USD) |
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C8051F340-GQR |
Silicon Labs |
8-bit Microcontrollers (MCU) 48 MIPS 64KB 10ADC |
Data Sheet |
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Negotiable |
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